Power control device of alternator for vehicle

ABSTRACT

The present invention relates to a device which supplies a field current to the field coil of an alternator for a vehicle in a gradually changing manner. In the device, a pulse voltage which has a pulse width corresponding to a phase difference between output signals of first and a second counters (15 and 16) is generated by a maximum duty ratio limiting circuit (19). When the alternator output voltage becomes higher than a reference voltage, the full-scale count time of the second counter is shortened relative to the full-scale count time of the first counter. On the other hand, when the output voltage becomes lower than the reference voltage, the same is elongated to thereby increase the phase difference. A switching transistor (12) is provided to control the field current supplied to the alternator field coil in response to the above pulse voltage.

TECHNICAL FIELD

The present invention relates to a power control device of an alternatorfor a vehicle which controls the field current and prevents abruptincrease in the torque of the alternator when an electric load isconnected to the alternator.

BACKGROUND ART

Such a device is disclosed in Japanese patent unexamined publication Sho62-64299 and its U.S. Pat. No. 4,636,706 to Bowman as one of theconventional power control devices of alternators.

However, the device disclosed in the above publication is equipped withan up-down counter (a binary counter which can count up and down) whichis controlled according to a result of comparison of an output voltageof an alternator with a reference voltage and a PWM circuit (pulse widthmodulation circuit) which includes a down-counter and generates pulsesignals having pulse width changing according to the number counted bythe up-down counter to supply a field current to the alternator fieldcoil. Therefore, many digital circuit elements are required and,consequently, the digital circuit becomes complicated.

Another object of the present invention is to provide a simple digitalcircuit which changes the field current gradually.

Another object of the present invention is to provide means forcontrolling the field-current switching means to have differentconducting times between increasing the field current and decreasing thefield current without difficulty.

A further object of the present invention is to provide means forcontrolling the field current switching means to synchronize an outputtiming of comparison between the alternator output voltage and areference voltage with the switching timing of the field-currentswitching means so that the switching means can switch on or offsteadily even under an abrupt output voltage change.

DISCLOSURE OF THE INVENTION

The power control device of an alternator for a vehicle according to thepresent invention comprises an alternator driven by an engine forsupplying electric current to vehicle electric loads, a comparator forcomparing an alternator output voltage with a reference voltage, anoscillator-couple having first and second oscillators for generatingoscillating signals having a phase difference therebetween which variesaccording to the output signal of the comparator, switching means forcontrolling the field current in response to the phase differencesupplied to the alternator field coil when an electric signal is appliedthereto, and a phase difference control circuit for shortening theoscillation cycle of the second oscillator relative to the oscillationcycle of the first oscillator to decrease the phase difference betweenthe signals of the first and the second oscillators when the alternatoroutput voltage, becomes higher than a reference voltage and forelongating the oscillation cycle of the second oscillator relative tothe oscillation cycle of the first oscillator thereby to increase thethe phase difference between the signals of the first and secondoscillators when the alternator output voltage becomes lower than thereference voltage, thereby increasing the phase difference.

According to the above structure, when the alternator output voltagebecomes higher than the reference voltage, the phase difference betweenthe oscillating signals of the two oscillators is controlled shorter. Onthe other hand, when the alternator output voltage becomes lower thanthe reference voltage, the switching means is made conductive by anelectric signal having a pulse width corresponding to the phasedifference. Thus, the abrupt increase of the generation torque can beprevented. Thereafter, the phase difference between the two oscillationsignals gradually increases and the conduction rate of the switchingmeans increases.

According to the present invention as described above, the pulse widthof the electric signal can be controlled by the phase difference betweenthe two oscillation signals, and the up-down counter is not necessaryand the circuit can be made simpler.

The device according to the present invention is characterized in thatthe electric signal is applied to the switching means in synchronismwith the signal of the first oscillator, or the second oscillator and atleast either the shortening or elongating of the oscillating cycle ischanged once in a plurality of times the electric signal is applied tothe switching means, thereby to achieving gradual supply of the fieldcurrent.

The device according to the present invention is characterized in thatthe switching means is opened when the alternator output voltage becomeshigher than the reference voltage to interrupt the field current withoutdelay.

The device according to the present invention generates a first pulsesignal according to the output signal of the comparator, and obtainslogical multiplication (AND) of the first pulse signal and the secondpulse signal having pulse width responsive to the phase difference tocontrol the switching means according to the AND signal, therebyinterrupting the field current without delay.

The device according to the present invention comprises an alternatordriven by an engine for supplying electric current to vehicle electricloads, a comparator for comparing an alternator output voltage with areference voltage, first and second counters for counting by a clock, amaximum duty-ratio limiting circuit generating a pulse signal having apulse width corresponding to the difference between timings ofoutputting the numbers counted by the respective counters, a switchingmeans for switching on and off the field current in response to thepulse signal of the maximum duty-ratio limiting circuit, and a phasedifference changing circuit for shortening the full-scale count time ofthe second counter relative to the full-scale count time of the firstcounter thereby to decrease the phase difference when the alternatoroutput voltage becomes higher than the reference voltage and forelongating the full-scale count time of the second counter relative tothe count time of the first counter thereby to increase the phasedifference when the alternator output voltage becomes lower than thereference voltage, thereby increasing the phase difference.

According to the above structure, the pulse width of the electric signalcan be controlled according to the phase difference of the two countersso that the up-down counter can be omitted and the circuit becomessimple.

Further, the device according to the present invention is characterizedin that the full-scale count time of the first counter is shortened by atiming signal which is obtained after a signal synchronized with theoutput pulse signal of the maximum duty-ratio limiting circuit isdivided several times to increase the phase difference, thereby enablingthe gradual increase of the field current.

Furthermore, the device according to the present invention ischaracterized in that the full-scale count time of the second counter isshortened by a timing signal synchronized with the counting of thesecond counter so that the phase difference is decreased more frequentlythan it is increased, thereby differentiating the speed of changes inthe pulse width between increasing and decreasing thereof with ease.

In addition, the device according to the present invention comprises areset determination circuit for resetting the first counter insynchronism with the timing signal to shorten the full-scale count timeof the first counter and to increase the phase difference, therebyenabling the gradual increase of the field current.

Still further, the device according to the present invention comprises areset determination circuit for resetting the second counter insynchronism with the timing signal to shorten the full-scale count timeof the first counter and to decrease the phase difference, therebydecreasing the maximum duty ratio.

Still further, the device according to the present invention ischaracterized in that the clock signal applied to the second counter iscontrolled according to logical multiplication of the timing signal,which is obtained after the output signal of the first counter isdivided several times and the output signal of the first counter,thereby increasing the full-scale count time of the second counterrelative to the full-scale count time of the first counter so as toincrease the phase difference, enabling a gradual increase of the fieldcurrent.

Still further, in the device according to the present invention, themaximum duty-ratio limiting circuit comprises a flip-flop circuit whichis set at a given number of the first counter and reset at a givennumber of the second counter, thereby providing a simple circuit.

Still further, the device according to the present invention comprises aconstant frequency circuit for generating a second pulse signal having apulse width which varies according to the output of the comparator insynchronism with the output pulse signal of the maximum duty-ratiolimiting circuit, and a reset determination circuit for determiningdecreases of the phase difference in response to the conditions of thefirst and second pulse signals when the second counter counts a givennumber, whereby steady switching operation is ensured even when anabrupt change of the output voltage takes place.

Furthermore, the device according to the present invention comprises aconstant frequency circuit for setting a reference level in synchronismwith the output pulse signal of the maximum duty-ratio limiting circuitand for generating an output which is a result of comparison of thereference level and a smoothed or an average level of the output of thecomparator, whereby the switching means is controlled according to theoutput signal of the constant frequency circuit, thereby ensuringreliable control of the switching means.

Still further, the device according to the present invention comprisesan AND circuit for producing logical multiplication of the output signalof the maximum duty ratio limiting circuit and the output signal of thecomparator and for controlling the switching means, whereby fastswitching operation of the field current is ensured.

Still further, in the device according to the present invention, theswitching means is opened when said alternator output voltage becomeshigher than said reference voltage, whereby fast switching operation ofthe field current is ensured.

Still further, the device according to the present invention comprisesan alternator driven by an engine for supplying electric current tovehicle electric loads, a comparator for comparing an alternator outputvoltage with a reference voltage, first and second counters for countingby a clock, a maximum duty-ratio limiting circuit generating a pulsesignal having a pulse width corresponding to a time difference betweenoutput signals of the respective counters, a switching means forswitching on or off the field current in response to the pulse signal ofthe maximum duty-ratio limiting circuit, and a time differencedetermination circuit for determining the time difference between theoutput signals of the first and second counters according to comparisonof the alternator output voltage and the reference voltage.

As a result, the pulse width of the electric signal can be determined inaccordance with the phase difference between the two signals of thecounters, thereby omitting the up-down counter and making the circuitsimple.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a device according to an embodiment ofthe present invention. FIG. 2 is a circuit diagram of a main part of theabove embodiment. FIG. 3 is a time chart showing the operation of theabove embodiment. FIG. 4 is a time chart showing the operation of theabove embodiment. FIG. 5 is a circuit diagram according to a secondembodiment of the present invention. FIG. 6 is a time chart showingoperation of the above embodiment.

BEST MODE OF CARRYING OUT THE INVENTION

The invention is described in more detail with reference to Figures,next.

An embodiment is described with reference to FIG. 1 and FIG. 2. Areference numeral 1 is a voltage regulator (regulator), which detects acharging voltage of a battery 3 charged by an alternator 2. In theregulator 1, a comparator 11 disconnects a transistor (Tr) 12 whichcomposes a switching means controlling a field current supplied to afield coil 21 of the alternator 2 when a detected charging voltage isgreater than a reference voltage Vr. An power supply 10 of the regulator1 is connected to the battery 3 through a key switch 5.

A reference numeral 15 is a first binary counter. The counter is n-stagecounter, which starts to count from 2° up to 2^(n) and returns 2°, andgenerates a clock signal(CK2) having a cycle TK2=TK1×2^(n) insynchronism with a clock signal CK1 generated by an oscillator 14(having a cycle TK1).

A reference numeral 16 is a n-stage second binary counter which countsin synchronism with the clock signal CK1 in the same manner as the firstbinary counter 15.

A reference numeral 19 is a hold circuit. The circuit composes a maximumduty ratio limiting circuit which generates a pulse signal according toa phase difference between the first and second counters. The holdcircuit 19 includes a SR flip-flop circuit which is set to generate Hisignal when the first counter 15 counts a first given number and isreset to generate Lo signal when the second counter 16 counts a secondgiven number. In case the SR flip-flop circuit 19 is set when the firstcounter 15 counts 2^(n) and, thereafter, it is reset when the secondcounter 16 counts 2°, the set time is (k+1)×TK1 at the cycle TK2,wherein k is a count number corresponding to a phase difference betweenthe first and the second counters. Then, the transistor 12 is madeconductive by the output of the AND circuit 13 which is applied at itsinput terminals an output of a terminal Q of the hold circuit 19 and anoutput of the voltage detecting comparator 11. Thus, the maximumduty-ratio is limited to (k+1)×TK1/TK2=(k+1)/2^(n).

A reference numeral 17 is a reset determination circuit which shortensthe full-scale count time of the first counter 15 when a detectedcharging voltage of the battery 3 is lower than the reference voltage Vrso that the phase difference between the first and the second counters15 and 16 is increased.

A reference numeral 18 is a frequency dividing circuit which controlsthe reset determination circuit 17 to limit the timing of increasing thephase difference between the first and the second counters 15 and 16.The frequency dividing circuit 18 includes an m-stage binary counter andreduces the frequency of increasing the phase difference to 1/2^(m) (asshown in FIG. 3).

The operation of the above embodiment is described next.

When the charging voltage of the battery 3 is lower than the referencevoltage Vr, the output signal Ss of the comparator 11 becomes Hi.Accordingly, the conduction of the transistor 12 is controlled by theoutput signal of the Q terminal of the hold circuit 19. The hold circuit19 is set when the count number of the first counter 15 becomes 2^(n)(CK2) and the output signal of the terminal Q becomes Hi. Thereafter, itis reset by the 2° signal of the second counter 16 and the output signalof the Q terminal becomes Lo. When the count phase of the first counter15 leads by a number k ahead of the second counter, the output signal ofthe Q terminal of the hold circuit 19 holds the Hi signal until itcounts as many as (k+1).

When the count number of the first counter 15 becomes 2^(n), the outputsignal of the hold circuit 19 becomes Hi and, consequently, the outputsignal of the AND circuit 13 becomes Hi. At this moment, an AND circuit172 (shown in FIG. 2) generates an output signal Hi while the signal CK3is Hi, thereby to reset the counter 15 to the number 2° (as shown inFIG. 4). That is, the counting of the first counter 15 leads one timeahead and the phase of the number counted by the counter 15 leads sothat the phase difference between the first counter 15 and the secondcounter 16 increases.

Accordingly, the output signal (maximum duty ratio signal SA) of thehold circuit 19 becomes Hi for a period corresponding to (k+2) and theduty ratio of the transistor 12 increases to (k+2)/2^(n) from(k+1)/2^(n). As the duty ratio of the transistor 12 increases at a rate1/2^(n) each cycle CK3, the field current increases gradually and thegenerating torque and the output current of the alternator 2 increasegradually.

When the charging voltage of the battery 3 is higher than the referencevoltage Vr, the output signal Ss of the comparator 11 becomes Lo, theAND circuit 13 outputs the Lo signal and the transistor 12 is turnedoff, thereby to decrease the output current of the alternator. At thisstage, when the second counter has counted 2^(n), a Hi signal is appliedto the non-inverting input terminal of the AND circuit 171 while a Losignal is applied from the AND circuit 13 to the inverting terminalthereof, thereby resetting the second counter 16 to 2°. Therefore, thecounting of the second counter 16 is brought forward by one time and thephase of the counter 16 advances, thereby decreasing the phasedifference between the counting of the first and the second counters. Asa result, the duty ratio of the output signal (maximum duty ratio signalSA) of the hold circuit 19 is decreased.

If the phase difference is further controlled to decrease while thephase difference between the counting of the first and the secondcounters has been at a minimum, the duty ratio may change from a minimumto a maximum. On the other hand, if the phase difference is furthercontrolled to increase while the phase difference between the countingof the first and the second counters has been at a maximum, the dutyratio may change from the maximum to the minimum. In order to preventthe above inconvenience, means for limiting the range of phasedifference may be provided.

Another embodiment is described with reference to FIG. 5 and FIG. 6. Inorder to increase the phase difference, the counting of the secondcounter 16 is stopped once in this embodiment although the counting ofthe first counter 15 is advanced in the above embodiment.

The phase difference may be increased without regard to the detectedvoltage of the battery 3, however the increasing speed thereof is lowsince the counter increments by 1 at a cycle CK3. On the other hand,since the phase difference is decreased by one count in a cycle of CK2,the decreasing speed is (2^(m) -1) times as fast as the increasingspeed. Therefore, if the frequency divider circuit 18 is one stage type,the increasing speed is the same as the decreasing speed, and if thefrequency divider circuit 18 has more than two stages, the increasingspeed becomes lower than the decreasing speed.

The embodiment has an averaging circuit (a resistor 111 and a capacitor112) which averages the difference between the detected voltage of thebattery 3 and the reference voltage Vr and generates an average voltage.The average voltage is compared with a saw tooth voltage wave which issynchronized with the signal CK2 and formed into a constant frequencysignal Ss which is synchronized with the signal CK2. The signal Ssbecomes Hi in synchronism with the rise-up of the signal CK2 when atransistor 115 is made conductive. If the signal Ss becomes Lo beforethe second counter 16 becomes 2°, the counting by the second counter 16is carried one time ahead, thereby advancing the phase. Since the phaseof the counter 16 loses one count in each cycle of the signal CK3, thephase of the counter 16 is controlled so that the duration in which thesignal Ss stays Hi becomes a period in which the output signal CK2 ofthe counter 15 rises up and the count number of the second counter 16becomes 20°. The output signal of the terminal Q of the hold circuit 19(maximum duty ratio signal SA) is set when the signal CK2 rises up andreset when the second counter 16 counts 2² so that the duty ratio (DA)of the output signal (maximum duty ratio signal SA) of the Q terminal ofthe hold circuit become greater than the duty ratio (Ds) of the signalSs (that is, DA=Ds+2² /2^(n)). As a result, when the alternator runsunder a normal operation, no limitation by the maximum duty ratio signalis applied. Even if the electric load connected to the alternatorchanges in some degree, the conducting period of the transistor 12 canchange within a ratio 2² /2^(n) immediately (since it is not limited bythe maximum duty ratio signal) and no trouble of the voltage drop (e.g.dimming of the head lights) due to shortage of the output current of thealternator is expected.

In case the electric load increases significantly, the maximum dutyratio signal SA limits the increase of the duty ratio of the transistor12.

The transistor 12 may be controlled by the maximum duty ratio limitingcircuit (hold circuit 19) shown in FIG. 2.

INDUSTRIAL APPLICABILITY

As described above, the power control device of the alternator for avehicle according to the present invention is most appropriate to adevice for controlling the field current supplied to the field coil ofthe vehicle alternator by a digital circuit.

We claim:
 1. A power control device of an alternator for a vehiclecomprising:an alternator driven by an engine for supplying electriccurrent to vehicle electric loads, a comparator for comparing analternator output voltage with a reference voltage, an oscillator-couplehaving first and second oscillators for generating oscillating signalshaving a phase difference therebetween which varies according to anoutput signal of said comparator; switching means for controlling afield current according to a signal having a pulse width which varies inresponse to said phase difference, and a phase difference controlcircuit for decreasing an oscillation cycle of said second oscillatorrelative to an oscillation cycle of said first oscillator when saidalternator output voltage becomes higher than said reference voltagethereby to decrease a phase difference between said oscillating signals,and increasing said oscillation cycle of said first oscillator when saidalternator output voltage becomes lower than said reference voltagethereby to increase said phase difference.
 2. A power control device ofan alternator for a vehicle claimed in claim 1, wherein said phasedifference control circuit supplies an electric signal to said switchingmeans in synchronism with said signal of said first oscillator or saidsecond oscillator and changes at least either one of said decreasing andincreasing of the oscillating cycle once in a plurality of times saidelectric signal is applied to said switching means.
 3. A power controldevice of an alternator for a vehicle as claimed in claim 1 or claim 2,wherein said phase difference control circuit opens said switching meanswhen said alternator output voltage becomes higher than said referencevoltage to interrupt said field current.
 4. A power control device of analternator for a vehicle as claimed in claim 1 or claim 2, wherein saidphase difference control circuit generates a first pulse signalaccording to said output signal of said comparator, and obtains an ANDoutput signal of said first pulse signal and said second pulse signalhaving a pulse width responsive to the phase difference to control theswitching means according to said AND output signal, thereby controllingsaid switching means.
 5. A power control device of an alternator for avehicle comprising:an alternator driven by an engine for supplyingelectric current to vehicle electric loads, a comparator for comparingan alternator output voltage with a reference voltage, first and secondcounters for counting by a clock, a maximum duty-ratio limiting circuitgenerating a pulse signal having a pulse width corresponding to a phasedifference between output signals of said respective counters, aswitching means for switching on or off the field current in response tosaid pulse signal of said maximum duty-ratio limiting circuit, and aphase difference changing circuit for shortening a full-scale count timeof said second counter relative to a full-scale count time of said firstcounter when the alternator output voltage becomes higher than saidreference voltage thereby to decrease said phase difference, and forelongating said full-scale count time of said second counter relative tosaid full-scale count time of said first counter when said alternatoroutput voltage becomes lower than said reference voltage thereby toincrease said phase difference.
 6. A power control device of analternator for a vehicle claimed in claim 5, wherein said phasedifference changing circuit shortens said full-scale count time of saidfirst counter in response to a timing signal which is obtained after asignal synchronized with an output pulse signal of said maximumduty-ratio limiting circuit is divided several times to increase saidphase difference.
 7. A power control device of an alternator for avehicle claimed in claim 6, wherein said phase difference changingcircuit shortens said full-scale count time in response to a timingsignal synchronized with a number counted by said second counter so thatsaid phase difference is decreased more frequently than it is increased.8. A power control device of an alternator for a vehicle claimed inclaim 6, wherein said phase difference changing circuit comprises areset determination circuit for resetting said first counter insynchronism with said timing signal to shorten said full-scale counttime of said first counter and to increase said phase difference.
 9. Apower control device of an alternator for a vehicle claimed in claim 7,wherein said phase difference changing circuit comprises a resetdetermination circuit for resetting the second counter in synchronismwith said timing signal to shorten said full-scale count time of saidsecond counter and to decrease said phase difference.
 10. A powercontrol device of an alternator for a vehicle claimed in claim 5,wherein said phase difference changing circuit comprises means fordividing said output signal of said first counter several times toproduce a timing signal and provides a logical multiplication of saidtiming signal and output signal of the first counter to obtain a clocksignal applied to the second counter, thereby increasing the full-scalecount time of the second counter relative to the full-scale count timeof the first counter and to increase the phase difference.
 11. A powercontrol device of an alternator for a vehicle claimed in claim 5,wherein said maximum duty ratio limiting circuit comprises a flip-flopcircuit which is set at a given number counted by the first counter andreset at a given number counted by the second counter.
 12. A powercontrol device of an alternator for a vehicle claimed in claim 5 furthercomprising a constant frequency circuit for generating a second pulsesignal having a pulse width which varies in response to the output ofthe comparator in synchronism with the output pulse signal of themaximum duty-ratio limiting circuit and a reset determination circuitfor determining the decrease of said phase difference according toconditions of the first and second pulse signal when the second countercounts a given number.
 13. A power control device of an alternator for avehicle claimed in claim 5 further comprising a constant frequencycircuit for setting a reference level in synchronism with said pulsesignal of said maximum duty ratio limiting circuit and comparing saidoutput signal of said comparator with said reference voltage togenerates a compared signal so as to control said switching means.
 14. Apower control device of an alternator for a vehicle claimed in claim 5further comprising an AND circuit for producing logical multiplicationof said output signal of said maximum duty ratio limiting circuit andsaid output signal of said comparator and for controlling said switchingmeans.
 15. A power control device of an alternator for a vehicle claimedin claim 5, wherein said phase difference changing circuit opens saidswitching means when said alternator output voltage becomes higher thansaid reference voltage.
 16. A power control device of an alternator fora vehicle comprising:an alternator driven by an engine for supplyingelectric current to vehicle electric loads, a comparator for comparingan alternator output voltage with a reference voltage, first and secondcounters for counting by a clock, a maximum duty-ratio limiting circuitgenerating a pulse signal having a pulse width corresponding to a timedifference between output signals of said respective counters, aswitching means for switching on or off the field current in response tosaid pulse signal of said maximum duty-ratio limiting circuit, and atime difference determination circuit for determining said timedifference between said output signals of said first and second countersaccording to comparison of said alternator output voltage and saidreference voltage.